The present invention relates to an electronic system and to a method for manufacturing three-dimensional, electronic systems and, in particular, to a method for a three-dimensional integration of electronic systems using preprocessed starting substrates.
A three-dimensional integration is generally a vertical arrangement of devices, wherein the vertical connection relates to a direction with regard to a surface or main face of a substrate or a wafer surface. The connection may here include both a mechanical and also an electrical connection.
In the course of continuous miniaturization and the compact implementation of integrated circuits it is getting more and more important to use available space as optimally as possible with devices or circuits. This simultaneously leads to an increase of the performance of such optimally implemented systems, in particular when highly integrable vertical contacts may be selected freely by the substrate. With a use of silicon, for example, these are so-called “through-silicon vias” (TSV).
Conventional methods of three-dimensional integration with freely selectable vertical contacts are based on two possibilities:                a) implementing vertical contacts (through-silicon vias) after a complete processing of the devices or the device substrates; and        b) manufacturing the vertical contacts as parts of the device manufacturing, i.e. after completing the so-called front-end-of-line processes (FEOL), however before the so-called back-end-of-line processes (BEOL).        
FEOL processes are generally all those processes which include processing the device in the substrate, but not implementing metallization and oxide layers which, for example, serve for contacting and connecting the devices and are part of the BEOL processes.
Examples for case a) are described in EP 070362 (Verfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur) and in EP 1171912 (Verfahren zur vertikalen Integration von elektronischen Bauelementen mittels Rückseitenkontaktierung). As mentioned above, in both cases the vertical contacts are made after the so-called FEOL processing. Case b) is described, for example, in Mater. Res. Soc. Symp. Proc. Vol. 970, p. 8. Implementing the vertical contacts here includes, for example, an etching process and a metallization (or generally filling up with conductive material) to make it electrically conductive.
One advantage of a method according to case a) compared to a method according to case b) is, for example, that the technology of device manufacturing is not influenced. Case b), however, is a method for a three-dimensional integration, in which the manufacturing of the vertical contacts is part of the device manufacturing, as the vertical contacts are made after the completion of the so-called FEOL processes, but before the BEOL processes. This is why methods according to b) are disadvantageous in so far as a complete compatibility of the implementation of the vertical contacts with the BEOL processes is necessitated. On the other hand, these methods are, however, advantageous in so far as the vertical through-contacting does not have to be realized by relatively thick dielectric layers separating different metal layers of the multi-layer metallization. In addition to the substrate, (for example a silicon substrate), only a relatively thin dielectric layer below the first metallization layer is affected by forming (e.g. by etching) the vertical contacts.